Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation

نویسندگان

  • Hui-Wen Tsai
  • Ming-Dou Ker
چکیده

A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in deep-submicron CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-lm CMOS process with only 1.2-V devices to serve a 2.5-V/1.2-V mixed-voltage interface, without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by simulation and experimental results with operating speed up to 133 MHz for PCI-X compatible applications. 2009 Elsevier Ltd. All rights reserved.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology

This paper presents a 1.2V/2.5V tolerant I/O buffer design with only thin gate-oxide devices. The novel floating N-well and gate-tracking circuits in mixed-voltage I/O buffer are proposed to overcome the problem of leakage current, which will occur in the conventional CMOS I/O buffer when using in the mixedvoltage I/O interfaces. The new proposed 1.2V/2.5V tolerant I/O buffer design has been su...

متن کامل

Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology

The novel 2xVDD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1xVDD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2xVDD tolerant capability. Thus, the new 2xVDD logic gates can be operated under 2xVDD voltage environment without suffering the gate-oxide reliability issue.

متن کامل

A Low Noise and Reliable CMOS I/O Buffer for Mixed Low Voltage Applications

Abstract: In this paper the design of a high voltage tolerant and reliable CMOS I/O buffer is proposed without using thick-oxide devices. In this presented design for mixed low voltage interface applications, it uses a simpler structure and therefore the circuit has good gate-oxide reliability. In addition, it is free of dc leakage current. No additional pad for dual power supplies is required ...

متن کامل

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-achip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the desig...

متن کامل

Product Level Reliability Challenges for 65nm Technologies

We present a comprehensive review of product level reliability challenges for the 65nm technology node. The major reliability degradation mechanisms are analyzed for CMOS technologies. Historical data will show that hot carrier degradation has lost on importance and that negative bias temperature instability (NBTI) is the leading reliability concern for the 65nm technology node. Additionally, d...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:
  • Microelectronics Reliability

دوره 50  شماره 

صفحات  -

تاریخ انتشار 2010